1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to the formation of dielectric material layers of reduced permittivity.
2. Description of the Related Art
Semiconductor devices and any other microstructures are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently being, and in the foreseeable future will be, manufactured on the basis of silicon, due to the virtually unlimited availability of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable carriers for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs) and the like. The individual integrated circuits are arranged in an array, wherein most of the manufacturing steps, which may involve several hundred individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economic constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield. On the other hand, device dimensions are continuously reduced in view of performance criteria, as, typically, reduced transistor dimensions provide an increased operating speed.
In modern integrated circuits, the circuit elements are formed in and on a semiconductor layer, while most of the electrical connections are established in one or more “wiring” layers, also referred to as metallization layers, wherein the electrical characteristics, such as resistivity, electromigration, signal propagation delay, etc., of the metallization layers significantly affect the overall performance of the integrated circuit. Due to the ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper, in combination with a low-k dielectric material, has become a frequently used alternative in the formation of the wiring structures comprising the metallization layers having metal line layers and intermediate via layers. Metal lines act as intra-layer connections and vias act as inter-layer connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other are necessary to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the circuit elements, for instance by silicon-based field effect transistors, but is limited, owing to the increased density of circuit elements, which requires an even more increased number of electrical connections for mutually connecting these circuit elements, by the close proximity of the metal lines, since the line-to-line capacitance increases as the spacing between the metal lines decreases. For example, in presently available devices produced by volume production techniques, the distance between neighboring metal lines may be 100 nm and less in some metallization levels. This fact in combination with a reduced conductivity of the lines due to a reduced cross-sectional area results in increased RC (resistance capacitance) time constants. For this reason, traditional dielectrics, such as silicon dioxide (k>4) and silicon nitride (k>6-7) are increasingly replaced in metallization layers by dielectric materials having a lower permittivity, which are therefore also referred to as low-k dielectrics having a relative permittivity of approximately 3 or less.
However, in very advanced semiconductor devices with reduced distances between neighboring metal lines, such as the 45 nm technology node, the resulting parasitic RC time constants may still be considered inappropriate, thereby requiring even lower values for the dielectric constant of the inter metal dielectric material. For this purpose, the dielectric constant may further be reduced to values of 2.7 and less, in which case such dielectric materials may also be referred to as ultra low-k (ULK) materials. Thus, great efforts have been made in developing materials and corresponding manufacturing techniques usable in high volume production. To this end, a plurality of spin-on processes, in combination with corresponding polymer materials, may frequently be used, while, in other approaches, plasma enhanced chemical vapor deposition (CVD) techniques have been proven to be promising techniques for providing low-k dielectric materials. For example, in many approaches, the basic dielectric constant of a plurality of CVD deposited low-k dielectric materials may further be reduced by reducing the material density, which may frequently be accomplished by incorporating so-called porogens, i.e., organic materials including methyl groups that may be removed, at least partially, after the deposition so as to produce a porous dielectric material having the desired reduced dielectric constant.
For example, a plurality of process techniques have been established in which hydrogen-containing organic silicon materials may be provided to act as a basic low-k dielectric material and thus as a backbone for ULK materials, while additionally appropriate precursor species may be introduced into the deposition ambient during the plasma enhanced CVD process in order to incorporate volatile components into the basic low-k dielectric material. After deposition of the low-k dielectric material, a further treatment, such as a treatment based on ultraviolet light, may be performed so as to specifically break up chemical bonds of the porogens and to cause out-diffusion of the corresponding modified molecules, thereby generating respective nano voids in the basic low-k dielectric material.
Although the deposition of low-k dielectric materials by means of plasma enhanced CVD techniques has proven to be a very promising approach for sophisticated semiconductor devices, it turns out, however, that a further reduction of the dielectric constant to a value of 2.7 and less on the basis of a single precursor material may be extremely difficult, while, in other approaches, a more complex deposition regime may be used on the basis of at least two different precursor materials, thereby also resulting in a complex manufacturing sequence which may additionally result in non-desired characteristics of the low-k dielectric materials, as will be described in more detail with reference to FIGS. 1a and 1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 which comprises a substrate 101 that may include any circuit elements, such as transistors, capacitors and the like. For convenience, any such circuit elements are not shown. The substrate 101 represents a bulk silicon substrate or an SOI substrate since, typically, complex integrated circuits produced by volume production techniques may be formed on the basis of a silicon material, as previously explained. Furthermore, a dielectric layer 102, which may be comprised at least partially of a low-k material or any other dielectric material, is formed above the substrate 101 and represents a portion of a metallization level or a contact structure of the semiconductor device 100. For example, a metal region 103 is formed in the dielectric layer 102 and represents any conductive device area, such as a contact area of a circuit element or a metal region of a metallization layer. The metal region 103 is separated from the material of the dielectric layer, if required, by a barrier layer 104, which is typically provided as a layer for reducing diffusion of metal atoms into the dielectric material 102 and also to reduce diffusion of atoms from the dielectric layer 102 into the metal region 103. Additionally, the barrier layer 104 may also enhance adhesion of the metal region 103 to the dielectric material of the layer 102. In sophisticated devices, the metal region 103 comprises copper and the barrier layer 104 may be formed from one or more layers including tantalum, tantalum nitride, titanium, titanium nitride and the like. Frequently, a dielectric barrier layer or cap layer 105 comprised of a dielectric material that substantially prevents diffusion of metal atoms of the metal region 103 into neighboring dielectric areas is provided, while, in other cases, the layer 105 may additionally have etch stop capabilities during the patterning of a further dielectric layer 106, which represents a layer of dielectric material having a desired reduced dielectric constant, as described above. For example, the dielectric barrier or cap layer 105 may comprise silicon nitride, silicon carbide, nitrogen-containing silicon carbide and the like, which may efficiently reduce copper diffusion and may also provide enhanced mechanical integrity and the desired etch stop capabilities. It should be appreciated that additional dielectric materials may also be provided between the dielectric layer 102 and the layer 106, if required. The layer 106 may be comprised of a mixture of silicon, oxygen, hydrogen and carbon which may thus form the basic material network of the layer 106, the density of which may further be reduced in a subsequent manufacturing stage by partially removing a porogen material 107 in order to obtain a dielectric constant of 2.7 and less, as may be required for an enhanced performance of the semiconductor device 100.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After forming the basic structures of any circuit elements in and above the substrate 101, the dielectric layer 102 and the metal region 103 are formed on the basis of well-established process techniques. Next, the dielectric barrier or cap layer 105 is deposited, for instance, by plasma enhanced CVD on the basis of well-established process recipes in order to form the desired composition of materials. Thereafter, the dielectric layer 106 is deposited by a plasma enhanced CVD process 108 in which a plasma ambient is established by applying an appropriate electromagnetic power with a frequency of 10-15 MHz, which may be capacitively or inductively coupled into the plasma ambient. During the deposition process, a first precursor, indicated as Precursor 1, for instance in the form of a silane derivative, a siloxane derivative and the like, is supplied to the plasma ambient in combination with any appropriate carrier gases, such as noble gases and the like, thereby obtaining reactive molecules in the ambient 108, which may deposit above the substrate 101, i.e., on the layer 105. For this purpose, a process temperature is selected to be above approximately 300° C., for instance in the range of 350-500° C., thereby forming a basic network in the form of the layer 106, which may provide the desired moderately low dielectric constant in combination with specific chemical and mechanical characteristics. Moreover, during the deposition process 108, a second precursor material, indicating as Precursor 2, is supplied in order to incorporate an organic species, such as a complex molecule including a methyl group, which may thus be incorporated into the basic network of the material generated on the basis of the first precursor species. Consequently, during the deposition process 108, the porogens 107 may be incorporated into the basic material of the layer 106 with a certain concentration that may strongly depend on the overall process parameters of the process 108. Hence, the overall characteristics of the layer 106 including the porogens 107 are to be established by controlling a plurality of process parameters, which relate to at least two different precursor materials which require different flow rates and specific ramp up times, stabilization phases and the like which contributes to the overall complexity of the deposition process 108. Furthermore, due to the presence of the precursor species 2, i.e., the precursor material producing the porogens 107, a significant portion of volatile deposition byproducts may also be present in the deposition ambient 108 and may thus contaminate the substrate 101 and other exposed surface areas of a process tool used to establish the ambient of the deposition process 108. Consequently, the conditions for depositing the layer 106 above the plurality of substrates 101 may also strongly depend on the history of the process tool and may thus require sophisticated cleaning processes on a regular basis, thereby contributing to a significantly reduced throughput of the corresponding deposition tools.
FIG. 1b schematically illustrates the semiconductor device 100 in a subsequent manufacturing stage in which the device 100, i.e., the layer 106, is exposed to ultraviolet (UV) radiation during a process 109, during which elevated temperatures, for instance in the range of 300-500° C., in combination with an appropriate gaseous ambient are established. For example, an “inert” gas ambient, for instance a noble gas ambient, a nitrogen ambient and the like, is established at a pressure of several Torr while UV radiation with a wavelength of 200 nm or less is applied in order to break up chemical bonds, thereby initiating out-diffusion of organic molecules 107A. Consequently, during the treatment 109, the initial density of the layer 106 is reduced, for instance by forming nano voids 106A, due to the out-diffusion of a part of the previously incorporated porogens 107 (FIG. 1a). Due to the reduction of the density, a certain degree of shrinkage 106S is thus caused during the process 109, which may result in a reduced layer thickness, while the chemical and mechanical characteristics of the final layer 106 may also be influenced by the degree of shrinkage 106S. For example, typically, shrinkage of approximately 15 percent or higher with respect to the initial volume or layer thickness may be observed during the process 109 in order to obtain a reduced dielectric constant of 2.6 and less. It should be appreciated that, due to the out-diffusion of the species 107A, a significant contamination of the corresponding process tool may also occur, thereby also requiring a frequent cleaning of the process tools. Hence, the treatment 109 in combination with the previously incorporated porogens 107 (FIG. 1a) may contribute to a significant degree of shrinkage and device and tool contamination, thereby reducing overall process throughput, while at the same time increasing complexity of controlling the overall process result, for instance in view of layer characteristics, such as final layer thickness, mechanical stability, chemical stability, dielectric constant and the like.
Consequently, although the above-described process sequence based on at least two different precursor materials may enable the formation of dielectric materials having a dielectric constant of 2.6 and less, the resulting increased high degree of process complexity in controlling the process results in combination with the requirement of frequent complex cleaning processes may render this concept less attractive. On the other hand, well-established process recipes for forming a silicon-based low-k dielectric material by using plasma enhanced CVD techniques on the basis of a single precursor material without incorporation of a porogen may not allow a further reduction of the dielectric constant to a value of approximately 2.6 and less.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.